The present invention relates to semiconductor device fabrication, and more particularly to a method of fabricating a polysilicon back-gated silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) in which a polysilicon back-gate controls the threshold voltage of the front-gated device. The present invention also relates to a back-gated SOI MOSFET device comprising, among other elements, a polysilicon back-gate that controls the threshold voltage of the device.
Simultaneous reduction of supply and threshold voltages for low-power silicon-on-insulator (SOI) CMOS design without suffering performance losses will eventually reach the limit of diminishing returns as static power dissipation becomes a significant portion of the total power equation. In order to meet the opposing requirements of high-performance during circuit/system active periods, and low-power, during circuit/system idle periods, a dynamic threshold voltage control scheme is needed.
For SOI metal oxide field effect transistors (MOSFETs), there are two modes of operation: 1) fully depleted, and 2) partially depleted channel region. In conventional strongly fully depleted SOI devices, the silicon film thickness is usually less than or equal to half the depletion width of the bulk device. The surface potentials at the front and back interfaces are strongly coupled to each other and capacitively coupled to the front-gate and substrate through the front-gate dielectric and the buried oxide, respectively. Therefore, the potential throughout the silicon film, and hence the charge, is determined by the bias conditions on both the front-gate and the substrate. By replacing the substrate with a back-gate, the device becomes a dual-gated device.
The fully depleted design is unique to SOI because the front-gate and the back-gate both have control of the charge in the silicon film. In the strongly partially depleted device, the back-gate or the substrate has no influence on the front surface potential. In the middle regime, the device is nominally partially depleted and can become fully depleted by applying bias, thus, coupling of the front and back surface potentials still occurs.
To date, no adequate dynamic threshold voltage control schemes are present in conventional SOI MOSFET devices; therefore, as these devices are continually being scaled down to smaller sizes, the devices will become extremely leaky when operating under low-power conditions, i.e., when the devices are idle.
In view of the state of the art mentioned above, there is a continued need for providing a SOI MOSFET device that includes a dynamic threshold voltage control scheme that works under circuit/system active periods, as well as circuit/system idle periods.
The present invention is directed to a SOI MOSFET device that includes a dynamic threshold voltage control scheme, which is suitable for both high-performance, i.e., circuit/system active periods, and low-power, i.e., circuit/system idle periods, applications. Specifically, the present invention provides a SOI MOSFET device comprising a polysilicon back-gate region which controls the threshold voltage of the front-gate. NMOS and PMOS back-gates are also present which are switched independently of each other and the back-gate. For high-performance and low-power applications, the threshold voltage would be raised during system/circuit idle periods to reduce the static leakage current, and lowered during circuit/system active periods to achieve high-performance.
In the device aspect of the present invention, a SOI MOSFET device is provided that comprises:
an implanted back-gate region located atop an oxide layer, wherein a surface portion of said implanted back-gate region includes a back-gate oxide formed thereon;
a body region located atop said back-gate oxide;
a gate dielectric located atop a surface portion of said body region; and
a polysilicon gate located atop a portion of said gate dielectric.
The present invention also provides a method of fabricating the above-mentioned SOI MOSFET device. The inventive method utilizes processing steps that are compatible with conventional CMOS processes. Specifically, the method of the present invention comprises the steps of:
providing a structure including at least a back-gate oxide located atop a Si-containing layer, said Si-containing layer is a component of a SOI wafer;
forming alternating regions of back-gate-STI and first polysilicon atop said back-gate oxide;
forming a second polysilicon layer atop said alternating regions of back-gate-STI and first polysilicon;
implanting a back-gate region into said polysilicon layers;
forming an oxide layer on said second polysilicon layer;
bonding a holding-substrate wafer to said oxide layer and flipping the bonded structure to expose layers of said SOI wafer;
removing selective layers of said SOI wafer stopping on said Si-containing layer;
converting a portion of said Si-containing layer into a body region; and
forming a gate dielectric and a polysilicon gate atop said body region.
Additional BEOL processing steps, as described herein below, can also be performed following polysilicon gate formation.